(1) Field of the Invention
The present invention relates to an integrated circuit device composed of a plurality of function macro cells and, more particularly, to an integrated circuit device comprising one or more macro cells (hereinafter referred to as "mega-macro") designed in advance as a library of a large scale standard function block, zero or more macro cell(s) (hereinafter referred to as "user-macro") structured by a combination of a plurality of standard basic cells, and an interface block composed of a plurality of cells designed as a library of a standard function block for transferring signals between external terminals and an internal region.
(2) Description of the Related Art
In the integrated circuit device in a standard cell system structured by wiring a mega-macro(s) and a user-macro(s), the following test is carried out in many cases. A certain mode is set to allot the terminals of macro cells (hereinafter simply called "macro") to external terminals of the integrated circuit device, respectively. A signal is applied to each of the macro terminals through each of the external terminals to directly observe the output from the external terminal. Thus, each of the macros can be individually tested. Hereinafter, such a testing method will be referred to as a "macro isolation test".
Now referring to the drawings, an explanation will be given on one example of the conventional integrated circuits capable of performing such macro isolation test.
FIG. 1 shows an arrangement of the conventional single chip integrated circuit device 1. As shown in FIG. 1, the integrated circuit 1 is composed of mega-macros 2, 3; a user-macro 6 and an input/output interface macro 7. The input/output interface macro 7 serves as an interface between external terminals (hereinafter referred to as "pins") of a chip of the integrated circuit device and gates within the chip. The input/output interface macro 7 is composed of input interface blocks 8, 9; an output interface block 10; and an input/output interface block 11, and these blocks serve to transfer signal between pins A, B, C and D and the gates concerned within the integrated circuit device 1.
The mega-macro 2 is provided with a single input terminal in1, a single input/output terminal io1, and two output terminals out1 and out2. For the purpose of clearly showing the attributes of these terminals, the mega-macro 2 is illustrated in such a form that a macro core 4 which is a body of the mega-macro is separated from the other buffer portions. Specifically, the input terminal in1 of the mega-macro 2 is connected with the terminal C1 of the macro core 4 through an input buffer 201; the input/output terminal io1 is connected with the terminals C3 and C4 of the macro core 4 through an input/output buffer 202; the first output terminal out1 is connected with the terminal C2 of the macro core 4 through an output buffer 203; and the second output terminal out2 is connected with the terminal C5 through an output buffer 204. It should be noted that the output at the output terminal out2 of the mega-macro 2 represents the input/output state at the input/output terminal io1; the signal level "High", i.e., "1" at the output terminal out2 represents an "input state" at the terminal io1 while the signal level "Low", i.e., "0" at the terminal out2 represents an "output state" of the output terminal out1. Hereinafter, the signal level "High" is referred to as simply "1" and the signal level "Low" is referred to as simply "0".
Likewise, the mega-macro 3 is also separated into the macro core 5 which is a body of the macro and other buffer portions. Specifically, the input terminal in1 of the mega-macro 3 is connected with the terminal C6 of the macro core 5 through an input buffer 301; the first output terminal out1 is connected with the terminal C7 through an output buffer 302; the second output terminal out2 is connected with the terminal C8 of the macro core 5 through a three-state output buffer 303; and the third output terminal out3 is connected with the terminal C9 through an output buffer 304. It should be noted that the output state at the output terminal out3 of the mega-macro indicates whether or not the second output terminal out2 is in its "high impedance state"; "1" at the output terminal out3 represents the high impedance state at the second output terminal out2 whereas "0" at the terminal out3 represents the level output state of "0" or "1" at the second output terminal out2.
FIG. 2 shows a conventional arrangement in which a test circuit 21 is added to the circuit 1 so that the macro isolation test can be made for the mega-macros 2, 3. In FIG. 2, an integrated circuit device 25 is the integrated circuit device 1 equipped with a macro isolation circuit.
In FIG. 2, a decoder 13 produces three separate signals M1TEST, M2TEST and NORMAL on the basis of signals inputted through input interface blocks 12.sub.1 and 12.sub.2 from pins T1 and T2 of the integrated circuit device 25. The signal M1TEST is "1" when the mega-macro 2 is to be isolatedly tested, the M2TEST is "1" when the mega-macro 3 is to be isolatedly tested, and the NORMAL is "1" at the normal state when the integrated circuit device 25 is placed in the state equivalent to the integrated circuit device 1. Thus, the inputs at the pins T1 and T2 define the isolation test states. Selectors 16, 17 and 18.sub.1 to 18.sub.3 in the test circuit 21 operate as follows. The selector 16 produces, at its output terminal O, the signal at its input terminal N in response to the signal M2TEST="0" and the signal at its input terminal M2 in response to the signal M2TEST="1", respectively. The selector 17 produces, at its output terminal O, the signal at its input terminal N in response to the signal M1TEST="0" and the signal at its input terminal M1 in response to the signal M1TEST="1", respectively. The selectors 18.sub.1, 18.sub.2 and 18.sub.3 produce, at their output terminals O, the signal at their input terminals N in response to the signal NORMAL="1", the signal at the input terminal M1 in response to the signal M1TEST="1" and the signal at their input terminals M2 in response to the signal M2TEST="1" , respectively.
The operation of the test circuit 21 in the integrated circuit device 25 will be explained.
In the state where the signal NORMAL="1", all the selectors 16, 17, 18.sub.1, 18.sub.2 and 18.sub.3 produce, at their output terminals O, the signal at their input signals N. Then, the signal M1TEST="0" and so the output from the three-state buffer 14 is at its high impedance state, so that the integrated circuit device 25 is substantially equivalent to the integrated circuit device 1.
In the state where the signal M1TEST="1", the selectors 17, 18.sub.1, 18.sub.2 and 18.sub.3 connect the input terminal in1 of the mega-macro 2 with the pin A, the first output terminal out1 with the pin C, and the input/output terminal io1 with the pin D through the input/output interface block 11 in a state where the input and output sides are separated from each other. Further, the second output terminal out2 of the mega-macro 2 is connected with the input/output control terminal 20 of the input/output interface block 11. And, the terminal out2 essentially represents the input/output state of the input/output terminal io1 so that the state of the pin D permits the states of both the terminals io1 and io2 to be recognized. Thus, the macro isolation test for the macro 2 can be made through the pins A, C and D.
In the state where the signal M2TEST="1", the selectors 16, 18.sub.1, 18.sub.2 and 18.sub.3 connect the terminals in1, out1 and out2 with the pins A, C and D, respectively. Further, the terminal out3 of the mega-macro 3 is connected with the input/output control terminal 20 of the input/output interface block 11 so that the states of the terminal out3 can be observed through the state of the pin D. Thus, the macro isolation test can be made through the pins A, C and D.
However, the conventional integrated circuit device including the macro isolation testing circuit has the following disadvantage.
As seen from FIG. 2, the selectors 16, 17, 18.sub.1 -18.sub.3 for macro isolation test are inserted between the macros shown in FIG. 1. This results In an inconvenience of signal propagation delay in the normal mode. Particularly, if there are a larger number of mega-macros to be subjected to the isolation test, the selectors included in the test circuit become large-scale and, thus, the influence of delay appearing in the normal mode is very serious. For this reason, designing based on careful consideration must be made for portions where there is a critical path and there is a need for a precise timing to be controlled owing to racing in order to prevent an adverse effect on these portions. This makes it very complicate to design the conventional macro isolation test. The conventional design for the macro isolation test is likely to produce some errors for a simple logic level (level in the logic design) as well as for the characteristic such as the critical path.
Further, the circuit diagram including a test circuit, which is accompanied by many additional circuits as shown in FIG. 2, is much more complicate and difficult to read than the circuit in the normal state as shown in FIG. 1, whereby it is difficult to analyze and debug the circuit.
As described above, the integrated circuit device adopting the conventional macro isolation testing technique gives a designer a heavy burden in the step of test designing so that the time required for developing the desired integrated circuit device is extended.